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STK14C88-3
256 Kbit (32K x 8) AutoStore nvSRAM
Features

Functional Description
The Cypress STK14C88-3 is a 256 Kb fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrapTM technology producing the world's most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
35 ns and 45 ns access times Automatic nonvolatile STORE on power loss Nonvolatile STORE under Hardware or Software control Automatic RECALL to SRAM on power up Unlimited Read/Write endurance Unlimited RECALL cycles 1,000,000 STORE cycles 100 year data retention Single 3.3V+0.3V power supply Commercial and Industrial Temperatures 32-pin (300mil) SOIC and 32-pin (600 mil) PDIP packages RoHS compliance
Logic Block Diagram
Quantum Trap 512 X 512
A5 A6 A7 A8 A9 A 11 A 12 A 13 A 14
VCC
VCAP
STORE ROW DECODER STATIC RAM ARRAY 512 X 512 RECALL
POWER CONTROL STORE/ RECALL CONTROL
HSB
SOFTWARE DETECT COLUMN I/O INPUT BUFFERS COLUMN DEC
A13 - A 0
DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
A 0 A 1 A 2 A 3 A 4 A 10
OE
CE WE
Cypress Semiconductor Corporation Document Number: 001-50592 Rev. **
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 29, 2009
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STK14C88-3
Pin Configurations
Figure 1. Pin Diagram - 32-Pin SOIC/32-Pin PDIP
Table 1. Pin Definitions - 32-Pin SOIC/32-Pin PDIP Pin Name A0-A14 DQ0-DQ7 WE CE OE VSS VCC HSB W E G Alt IO Type Input Input or Output Input Input Input Ground Input or Output Description Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. Bidirectional Data IO lines. Used as input or output lines depending on operation. Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO pins is written to the specific address location. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the IO pins to tri-state. Ground for the Device. The device is connected to ground of the system. Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected (connection optional).
Power Supply Power Supply Inputs to the Device.
VCAP
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements.
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STK14C88-3
Device Operation
The STK14C88-3 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture enables the storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM READ and WRITE operations are inhibited. The STK14C88-3 supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE operations. Figure 2. AutoStore Mode
SRAM Read
The STK14C88-3 performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A0-14 determines the 32,768 data bytes accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAA (READ cycle 1). If the READ is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (READ cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common IO pins DQ0-7 are written into the memory if it has valid tSD, before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.
WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. An optional pull-up resistor is shown connected to HSB. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. If the power supply drops faster than 20 us/volt before Vcc reaches VSWITCH, then a 1 ohm resistor should be connected between VCC and the system supply to avoid momentary excess of current between VCC and VCAP.
AutoStore Inhibit Mode
If an automatic STORE on power loss is not required, then VCC is tied to ground and +3.3V is applied to VCAP (Figure 3). This is the AutoStore Inhibit mode, where the AutoStore function is disabled. If the STK14C88-3 is operated in this configuration, references to VCC are changed to VCAP throughout this data sheet. In this mode, STORE operations are triggered through software control. It is not permissible to change between these options "On the fly".
AutoStore(R) Operation
The STK14C88-3 can be powered in one of three storage operations: During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. A charge storage capacitor having a capacity of between 68 uF and 220 uF (+20%) rated at 4.7V should be provided. To reduce unnecessary nonvolatile stores, AutoStore and Hardware Store operations are ignored, unless at least one
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STK14C88-3
Figure 3. AutoStore Inhibit Mode and share a single capacitor. The capacitor size is scaled by the number of devices connected to it. When any one of the STK14C88-3 detects a power loss and asserts HSB, the common HSB pin causes all parts to request a STORE cycle. (A STORE takes place in those STK14C88-3 that are written since the last nonvolatile cycle.) During any STORE operation, regardless of how it is initiated, the STK14C88-3 continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the STK14C88-3 remains disabled until the HSB pin returns HIGH. If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC < VRESET), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. If the STK14C88-3 is in a WRITE state at the end of power up RECALL, the SRAM data is corrupted. To help avoid this situation, a 10 Kohm resistor is connected either between WE and system VCC or between CE and system VCC.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14C88-3 software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. When a STORE cycle is initiated, input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following READ sequence is performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0FC0, Initiate STORE cycle The software sequence is clocked with CE controlled READs. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that READ cycles and not WRITE cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is again activated for READ and WRITE operation.
Hardware STORE (HSB) Operation
The STK14C88-3 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven LOW, the STK14C88-3 conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM takes place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition, while the STORE (initiated by any means) is in progress. Pull up this pin with an external 10K ohm resistor to VCAP if HSB is used as a driver. SRAM READ and WRITE operations, that are in progress when HSB is driven LOW by any means, are given time to complete before the STORE operation is initiated. After HSB goes LOW, the STK14C88-3 continues SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations take place. If a WRITE is in progress when HSB is pulled LOW, it allows a time, tDELAY to complete. However, any SRAM WRITE cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. The HSB pin is used to synchronize multiple STK14C88-3 while using a single larger capacitor. To operate in this mode, the HSB pin is connected together to the HSB pins from the other STK14C88-3. An external pull up resistor to VCAP is required, since HSB acts as an open drain pull down. The VCAP pins from the other STK14C88-3 parts are tied together
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STK14C88-3
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations is performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0C63, Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared, and then the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is once again ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times.
Low Average Active Power
CMOS technology provides the STK14C88-3 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 4 and Figure 5 show the relationship between ICC and READ or WRITE cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 3.6V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14C88-3 depends on the following items: 1. The duty cycle of chip enable 2. The overall cycle rate for accesses 3. The ratio of READs to WRITEs 4. CMOS versus TTL input levels 5. The operating temperature 6. The VCC level 7. IO loading Figure 4. Current Versus Cycle Time (READ)
Preventing STORE
The STORE function can be disabled on the fly by holding HSB high with a driver capable of sourcing 30 mA at a VOH of at least 2.2V, because it has to overpower the internal pull down device. This device drives HSB LOW for 20 s at the onset of a STORE. When the STK14C88-3 is connected for AutoStore operation (system VCC connected to VCC and a 68 F capacitor on VCAP) and VCC crosses VSWITCH on the way down, the STK14C88-3 attempts to pull HSB LOW. If HSB does not actually get below VIL, the part stops trying to pull HSB LOW and aborts the STORE attempt.
Hardware Protect
The STK14C88-3 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low voltage conditions. When VCAPNoise Considerations
The STK14C88-3 is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise.
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STK14C88-3
Best Practices
nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer's sites, sometimes, reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration and cold or warm boot status, should always program a unique NV pattern (for example, a complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final Table 2. Hardware Mode Selection CE H L L X L WE X H L X H HSB H H H L H A13 - A0 X X X X 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0FC0 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0C63 Mode Not Selected Read SRAM Write SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL IO Output High Z Output Data Input Data Output High Z Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Power Standby Active[1] Active ICC2[2] Active[1, 3, 4, 5] system manufacturing test to ensure these system routines work consistently. Power up boot firmware routines should rewrite the nvSRAM into the desired state. While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs or incoming inspection routines). The VCAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the max VCAP value because the higher inrush currents may reduce the reliability of the internal pass transistor. Customers who want to use a larger VCAP value to ensure there is extra store charge should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period.
L
H
H
Active[1, 3, 4, 5]
Notes 1. I/O state assumes OE < VIL. Activation of nonvolatile cycles does not depend on state of OE. 2. HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the part will go into standby mode, inhibiting all operations until HSB rises. 3. CE and OE LOW and WE HIGH for output behavior. 4. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle. 5. While there are 15 addresses on the STK14C88-3, only the lower 14 are used to control software modes.
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Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Temperature under bias.............................. -55C to +125C Supply Voltage on VCC Relative to GND ..........-0.5V to 7.0V Voltage on Input Relative to Vss............ -0.6V to VCC + 0.5V Voltage on DQ0-7 or HSB .......................-0.5V to Vcc + 0.5V Power Dissipation ......................................................... 1.0W DC output Current (1 output at a time, 1s duration) .... 15 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.0V to 3.6V 3.0V to 3.6V
DC Electrical Characteristics
Parameter ICC1 Description
Over the operating range (VCC = 3.0V to 3.6V) [6] Test Conditions Min Max 50 42 52 44 3 9 Unit mA mA mA mA mA mA Average VCC Current tRC = 35 ns Commercial tRC = 45 ns Dependent on output loading and cycle rate. Values Industrial obtained without output loads. IOUT = 0 mA. Average VCC Current All Inputs Do Not Care, VCC = Max during STORE Average current for duration tSTORE Average VCC Current WE > (VCC - 0.2V). All other inputs cycling. at tRC= 200 ns, 5V, Dependent on output loading and cycle rate. Values obtained without output loads. 25C Typical Average VCAP Current All Inputs Do Not Care, VCC = Max during AutoStore Average current for duration tSTORE Cycle Average VCC Current tRC=35ns, CE > VIH (Standby, Cycling TTL tRC=45ns, CE > VIH Input Levels) Commercial Industrial
ICC2 ICC3
ICC4 ISB1[7]
2
mA
18 16 19 17 1
mA mA mA
ISB2[7]
VCC Standby Current CE > (VCC - 0.2V). All others VIN < 0.2V or > (VCC - 0.2V). (Standby, Stable CMOS Input Levels) Input Leakage Current VCC = Max, VSS < VIN < VCC Off State Output Leakage Current Input HIGH Voltage Input LOW Voltage Output HIGH Voltage IOUT = -4 mA except HSB Output LOW Voltage Logic `0' Voltage on HSB output Storage Capacitor IOUT = 8 mA except HSB IOUT = 3 mA Between VCAP pin and Vss, 68 to 220uF +20%, 4.7V rated. 54 VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL -1 -1 2.2 VSS - 0.5 2.4
IIX IOZ VIH VIL VOH VOL VBL VCAP
+1 +1 VCC + 0.5 0.8
A A V V V
0.4 0.4 264
V V uF
Notes 6. VCC reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground. 7. CE > VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
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STK14C88-3
Data Retention and Endurance
Parameter DATAR NVC Data Retention Nonvolatile STORE Operations Description Min 100 1,000 Unit Years K
Capacitance
In the following table, the capacitance parameters are listed.[8] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 0 to 3.0 V Max 5 7 Unit pF pF
Thermal Resistance
Parameter
In the following table, the thermal resistance parameters are listed.[8] Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 32-SOIC TBD TBD 32-PDIP TBD TBD Unit C/W C/W
JA JC
Figure 6. AC Test Loads R1 317 3.3V Output 30 pF R2 351
AC Test Conditions
Input Pulse Levels .................................................. 0 V to 3 V Input Rise and Fall Times (10% - 90%)........................ <5 ns Input and Output Timing Reference Levels ................... 1.5 V
Note 8. These parameters are guaranteed by design and are not tested.
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AC Switching Characteristics
SRAM Read Cycle
Parameter Cypress Alt Parameter tACE tELQV [9] tAVAV, tELEH tRC tAA [10] tAVQV tDOE tGLQV tAXQX tOHA [10] tLZCE [11] tELQX tHZCE [11] tEHQZ [11] tGLQX tLZOE tHZOE [11] tGHQZ tPU [8] tELICCH tEHICCL tPD [8] 35 ns Description Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Min 35 35 15 5 5 13 0 13 0 35 0 45 0 15 5 5 15 Max 35 45 45 20 45 ns Min Max 45 Unit ns ns ns ns ns ns ns ns ns ns ns
Switching Waveforms
Figure 7. SRAM Read Cycle 1: Address Controlled [9, 10]
Figure 8. SRAM Read Cycle 2: CE and OE Controlled [9]
Notes 9. WE and HSB must be HIGH during SRAM Read Cycles. 10. I/O state assumes CE and OE < VIL and WE > VIH; device is continuously selected. 11. Measured 200 mV from steady state output voltage.
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Table 3. SRAM Write Cycle Parameter Cypress Alt Parameter tWC tAVAV tWLWH, tWLEH tPWE tELWH, tELEH tSCE tSD tDVWH, tDVEH tWHDX, tEHDX tHD tAVWH, tAVEH tAW tSA tAVWL, tAVEL tWHAX, tEHAX tHA [11,12] tWLQZ tHZWE tLZWE [11] tWHQX
35 ns Description Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active After End of Write Min 35 25 25 12 0 25 0 0 13 5 5 Max
45 ns Min 45 30 30 15 0 30 0 0 15 Max Unit ns ns ns ns ns ns ns ns ns ns
Switching Waveforms
Figure 9. SRAM Write Cycle 1: WE Controlled [13, 14]
tWC
ADDRESS
tSCE
CE
tHA
tAW tSA
WE
tPWE tSD tHD
DATA IN
DATA VALID
tHZWE
DATA OUT PREVIOUS DATA
HIGH IMPEDANCE
tLZWE
Figure 10. SRAM Write Cycle 2: CE Controlled [13, 14]
tWC
ADDRESS
CE
tSA tAW tPWE
tSCE
tHA
WE
tSD
DATA IN DATA VALID
tHD
DATA OUT
HIGH IMPEDANCE
Notes 12. If WE is Low when CE goes Low, the outputs remain in the high impedance state. 13. CE or WE must be greater than VIH during address transitions. 14. HSB must be HIGH during SRAM WRITE cycles.
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STK14C88-3
AutoStore or Power Up RECALL
Parameter tHRECALL [15] tSTORE [16, 17] tVSBL[16] VRESET VSWITCH tDELAY[16] Alt tRESTORE tHLHZ Description Power up RECALL Duration STORE Cycle Duration Low Voltage Trigger (VSWITCH) to HSB low Low Voltage Reset Level Low Voltage Trigger Level Time Allowed to Complete SRAM Cycle STK14C88-3 Min Max 550 10 300 2.4 2.7 2.95 1 Unit s ms ns V V s
tBLQZ
Switching Waveforms
Figure 11. AutoStore/Power Up RECALL
WE
Notes 15. tHRECALL starts from the time VCC rises above VSWITCH. 16. CE and OE low and WE high for output behavior. 17. HSB is asserted low for 1us when VCAP drops through VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB will be released and no store will take place.
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Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [18, 19] Parameter tRC[16] tSA
[18, 19]
Alt tAVAV tAVEL tELEH tELAX
Description STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration
35 ns Min 35 0 25 20 20 Max Min 45 0 30 20
45 ns Max
Unit ns ns ns ns
tCW[18, 19] tHACE[18, 19] tRECALL
20
s
Switching Waveforms
Figure 12. CE Controlled Software STORE/RECALL Cycle [19]
tRC
ADDRESS ADDRESS # 1
tRC
ADDRESS # 6
tSA
CE
tSCE
tHACE
OE
t STORE / t RECALL
DQ (DATA) DATA VALID DATA VALID
HIGH IMPEDANCE
Notes 18. The software sequence is clocked on the falling edge of CE without involving OE (double clocking will abort the sequence). 19. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
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Hardware STORE Cycle
Parameter tPHSB tDHSB tHLBL
[16, 20]
Alt tHLHX
Description Hardware STORE Pulse Width Hardware STORE Low to STORE Busy
STK14C88-3 Min 15 700 300 Max
Unit ns ns ns
tRECOVER, tHHQX Hardware STORE High to Inhibit Off
Switching Waveforms
Figure 13. Hardware STORE Cycle
Note 20. tDHSB is only applicable after tSTORE is complete.
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STK14C88-3
Part Numbering Nomenclature STK14C88- 3N F 45 I TR
Packaging Option: TR = Tape and Reel Blank = Tube
Temperature Range: Blank - Commercial (0 to 70C) I - Industrial (-40 to 85C)
Speed: 35 - 35 ns 45 - 45 ns
Lead Finish F = 100% Sn (Matte Tin) Package: N = Plastic 32-pin 300 mil SOIC W = Plastic 32-pin 600 mil DIP
Ordering Information
Speed (ns) 35 Ordering Code STK14C88-3NF35TR STK14C88-3NF35 STK14C88-3WF35 STK14C88-3NF35ITR STK14C88-3NF35I STK14C88-3WF35I 45 STK14C88-3NF45TR STK14C88-3NF45 STK14C88-3WF45 STK14C88-3NF45ITR STK14C88-3NF45I STK14C88-3WF45I Package Diagram 51-85127 51-85127 51-85018 51-85127 51-85127 51-85018 51-85127 51-85127 51-85018 51-85127 51-85127 51-85018 Package Type 32-pin SOIC 32-pin SOIC 32-pin PDIP 32-pin SOIC 32-pin SOIC 32-pin PDIP 32-pin SOIC 32-pin SOIC 32-pin PDIP 32-pin SOIC 32-pin SOIC 32-pin PDIP Industrial Commercial Industrial Operating Range Commercial
All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts
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Package Diagrams
Figure 14. 32-Pin (300 Mil) SOIC (51-85127)
PIN 1 ID
16 1
0.292[7.416] 0.299[7.594] 0.405[10.287] 0.419[10.642]
DIMENSIONS IN INCHES[MM] REFERENCE JEDEC MO-119
MIN. MAX.
17
32
PART # S32.3 STANDARD PKG. SZ32.3 LEAD FREE PKG.
SEATING PLANE
0.810[20.574] 0.822[20.878]
0.090[2.286] 0.100[2.540]
0.004[0.101] 0.050[1.270] TYP. 0.014[0.355] 0.020[0.508] 0.026[0.660] 0.032[0.812] 0.004[0.101] 0.0100[0.254]
51-85058 0.021[0.533] 0.041[1.041]
*A
0.006[0.152] 0.012[0.304]
51-85127-*A
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Package Diagrams (continued)
Figure 15. 32-Pin (600 Mil) PDIP (51-85018)
51-85018-*A
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STK14C88-3
Document History Page
Document Title: STK14C88-3 256 Kbit (32K x 8) AutoStore nvSRAM Document Number: 001-50592 Rev. ** ECN No. 2625096 Orig. of Change GVCH/PYRS Submission Date 12/19/08 New data sheet Description of Change
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(c) Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-50592 Rev. **
Revised January 29, 2009
Page 17 of 17
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